The invention relates generally to the field of testing of integrated circuit devices and, more particularly, to the testing of user-programmable or field programmable gate arrays (FLAGS).
In a field programmable gate array (FAA), the connections between the transistors, logic blocks, and input and output circuits are made by the user of this type of integrated circuit. The transistors, logic blocks, and input and output circuits are connected to line segments which intersect or abut each other at various points. At most of these points programmable elements known as antifuses are located to make a connection between the line segments if desired.
In an unprogrammed state, each antifuse remains in a high impedance, or "open circuit" state. When programmed, the antifuse is in a low impedance, or "closed circuit" state. The antifuses in the FPGA are selectively programmed by the user to make desired interconnections between the transistors, logic blocks and input and output circuits of the FPGA for a particular application. In this manner an FPGA is configured for a particular application.
It is thus highly desirable for a FPGA to be tested prior to its programming to check the functionality of the various elements of the FPGA, including its line segments and antifuses. Heretofore, if provisions had been made for the testing of a FPGA, special test transistors and circuits were added to the integrated circuit. These additions increased the complexity and space requirements for what is typically an already complex and crowded integrated circuit.
A typical FPGA integrated circuit has specified programming pins by which large voltages are introduced into the circuit for the programming of antifuses. In the FPGA of the present invention, the input/output buffer circuits are provided with a serial scan path for test signals according to the IEEE 1149.1 test standards. During the programming of the antifuses, signals in the 1149.1 serial scan path become control signals for the programming circuits which address wiring segments to specify the particular antifuses to be programmed while the programming voltages are supplied through the specified pins.
In accordance to the present invention, the programming circuits controlled by signals in the serial scan path and the specified programming pins are used to provide paths for testing the FPGA prior to the programming of the antifuses. In this manner the present invention is able to achieve the goals of testing the elements and functions of an FPGA with a minimal amount of additional transistors and circuits.